Analysis for Challenge 5

It was stated that the design center is 100μA for each transistor.  We here assume that IE~IC.  Thus the two emitter currents are also approximately 100μA at the design center.  Both emitter currents flow through R1.  Then, because the design center is 1.25V, and because VBE was declared to be 0.57V, R1 is calculated as follows:

R1 = (1.25V – 0.57V)/200μA

R1 = 3400 Ω

We notice that Q2 is 8 times larger than Q1.  Assuming identical emitter currents (and wafer processing, etc.), a general rule of thumb is that Q2‘s VBE will be reduced by 18mV for each factor of 2 size increase (see the note at the end of this section).  8X therefore implies a 54mV VBE reduction.  R2 “sees” this ΔVBE, and we can write

R2 = 0.054V/100μA

R2 = 540 Ω

And here is a sketch of the transfer characteristics. The key (the intuitive observation that must now be driven home) is this:  IC1 and IC2 cross over at the design center.  It is the crossover that allows completed reference circuits to find their respective design centers with the use of negative feedback.

Note:  The 18mV/octave rule can be derived from the Ebers-Moll model.