**Analysis for Challenge 5**

It was stated that the design center is 100μA for each transistor. We here assume that I_{E}~I_{C}. Thus the two emitter currents are also_{ }approximately 100μA at the design center. Both emitter currents flow through R1. Then, because the design center is 1.25V, and because V_{BE} was declared to be 0.57V, R_{1} is calculated as follows:

R_{1} = (1.25V – 0.57V)/200μA

R_{1} = 3400 Ω

We notice that Q_{2} is 8 times larger than Q_{1}. Assuming identical emitter_{ }currents (and wafer processing, etc.), a general rule of thumb is that Q_{2}‘s V_{BE} will be reduced by 18mV for each factor of 2 size increase (see the note at the end of this section). 8X therefore implies a 54mV V_{BE} reduction. R2 “sees” this ΔV_{BE}, and we can write

R_{2} = 0.054V/100μA

R_{2} = 540 Ω

And here is a sketch of the transfer characteristics.

The key (the intuitive observation that must now be driven home) is this: I_{C1} and I_{C2} *cross over* at the design center. It is the crossover that allows completed reference circuits to find their respective design centers with the use of negative feedback.

**Note**: The 18mV/octave rule can be derived from the Ebers-Moll model.

For more information place “Ebers-Moll model” in a search engine.

**Want to Know More About Bandgap References?**

A simplified circuit is located **here**.

A tutorial (specific to one particular voltage reference circuit element) is located **here**.

**For Additional Information**

Put “bandgap reference” into a search engine.

Put “Paul Brokaw” into a search engine.

**Want to Simulate This Challenge, But You Don’t Have a Simulator?**Try this one —> http://www.5spice.com/