## Circuit Challenge 9

Many years ago someone (whose name is now lost to antiquity) noticed that the circuit concept in Figure 1 could be used as a basic Digital-to-Analog Converter (DAC).  This DAC could, in turn, be embedded in a larger network and become an integral part of an Analog-to-Digital Converter (ADC).  If the capacitors were well-matched, if they had all been discharged, and if all the generators had been idling at 0V, then a step voltage on MSB (0V –> VREF) would result in a step voltage at VOUT (0V –> VREF/2).  In fact, if the generators were sequenced as a binary counter (0000 0000 –> 1111 1111) the output would display as a staircase.  With a well-controlled logic sequence, some comparator circuitry, a switch array, a stable voltage reference, and a register to latch the results, this circuit could be placed in a loop, and VOUT could be forced to “window in” on any arbitrary unknown voltage whose value lay reasonably in a range of 0V to VREF.  A latched digital word would then represent VUnknown.  A microprocessor would then evaluate that digital word. Figure 1

An analysis of the logic, the comparator circuitry, the voltage reference, etc. is not an object of this challenge.  We are here interested only in the capacitor array.  For those who want to “dive deep” into the particulars of over-all A-to-D structures, take heart:  This website will provide appropriate references in the online literature.  The assumption:  If you have made it this far in the challenges you have more than a casual interest in analog circuit theory.

Moving On

You want to integrate (on an IC) the capacitor array.  Two problems come to mind:

1.  Matching 128C to 1C could be a problem, especially if the
128C is one  structure.  If you argue that you could build
the 128C with 128 1Cs, you will then be confronted with
a stray capacitance problem related to interconnections.

2.  Even if you could  match the 128C to the 1C, the next
issue you confront will be total size.  Whatever the unit
C might be, the total  capacitance will be 256C.

Someone proposed the solution of Figure 2.  It was suggested that if CX is properly sized that VOUT from Figure 2 will perfectly  overlay VOUT from Figure 1, for the entire  staircase.  If this is true (and you hope it’s true), then the matching & sizing problems will be first-order obviated.  But is it true? Figure 2

The Challenge

The challenge is for you to derive a value for CX.  When you think you have it, click here.